In a CMOS image sensor seeking pixel miniaturization by adopting a multi-pixel shared structure, a method of reducing a drive load of pixels by installing a power source of each drain of a reset transistor and an amplifying transistor of the CMOS image sensor as a separate power source is known.
According to this method, compared with a case when the drain power source of the reset transistor and the drain power source of the amplifying transistor are driven by the same source, a capacity load of a vertical signal line becomes smaller so that a high-speed operation can be performed. In this method, however, a pulse enters the reset transistor of all pixels at the same time to drive the reset transistor and thus, the load of the drain power source of the reset transistor may become large.
The present patent is a patent that solves the above problem and further relates to an efficient pixel layout by sharing a drain diffusion layer of the reset transistor and a drain diffusion layer of the amplifying transistor by adjacent cells in different pixel sharing units to reduce the number of routing wires.